The present invention relates to a semiconductor device. It relates to a technology effectively applicable to a semiconductor device including a power semiconductor element represented by, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
In Japanese Unexamined Patent Publication No. 2001-94098 (Patent Document 1), there is described a technology of controlling the position for causing avalanche breakdown in a MOSFET using silicon carbide (SiC) as a constituent material. Specifically, in Patent Document 1, the surface layer part of the epitaxial layer is doped with carbon (C) as inactive ion species, and is doped with boron (B) as a conductive impurity, thereby to form a high concentration deep base layer; thus, avalanche breakdown is caused at the high concentration deep base layer.
Japanese Unexamined Patent Publication No. 7-58328 (Patent Document 2) describes the following technology: a p type SiC layer having a wide band gap is formed in the inside of an element region in which an IGBT used as a silicon constituent material is formed.
In Non-Patent Document 1, there is introduced an approximate expression giving the breakdown voltage of the pn junction for use in devices represented by MOSFET, IGBT (Insulated Gate Bipolar Transistor), and diode.
U.S. Pat. No. 5,441,901 (Patent Document 3) describes the following: the band gap may be set lower than that of silicon, or the band gap may be set higher than that of silicon by the concentration of carbon to be doped into silicon.